Interconnect structures for integrated circuits are conventionally made of aluminum doped with between 2 and 4% copper. In this case, the process includes depositing the metal, then etching it to form the interconnect network and finally deposit on top of it the dielectric which will serve both as lateral insulation of the lines and as vertical insulation of the metal levels. To improve the performance of the circuits, especially in terms of speed and consumption, copper interconnects are used. This is because, with the low resistively of copper, which is almost half that of copper-doped aluminum, such interconnects allow the resistances Rint to be reduced. A drawback with this approach is that copper is very difficult to etch.
A process, known as the damascene process, has therefore been developed and has replaced the etching of the metal. According to the damascene process, as described in Patent Application FR 2 794 286, trenches are firstly etched in a generally porous dielectric of low dielectric constant, then a diffusion barrier, made of a metal or a metal nitride (for example Ta, Ti, TiN, TaN), is deposited as a layer lining the walls of these trenches and then the interconnect metal is deposited in the trenches. Finally, the copper on the surface of the dielectric is “planed” by chemical-mechanical polishing (CMP) so as to leave metal only in the trenches.
However, during deposition of the metal barriers and then of the metal in the trenches etched in the dielectric, the metal may diffuse into the open pores thereof to a greater or lesser depth. Thus, there is a rapid change in the nature of the material, which then loses its insulating function. Furthermore, because of electronic component miniaturization, the metal lines are coming closer and closer together, being separated by a mean distance of the order of 0.1 μm. These small dimensions and the degradation of the dielectric mean that there is a risk of forming short circuits and of degrading the lateral capacitance between two metal lines. Such manifestations impair the proper performance of the electronic components produced.
Thus, it has been envisaged, as described in the Texas Instruments document “MRS Proc. Vol. 511, p. 213” to plug the open pores of the dielectric material using a layer of silicon oxide. However, with a conventional silicon oxide deposited by PECVD (Plasma Enhanced Chemical Vapour Deposition), the metal cannot be deposited properly because of the inhomogeneity of the silica layer. Another drawback associated with depositing an oxide layer is the degradation of the lateral capacitance between two metal lines, resulting in a stray capacitance, because of the high dielectric constant of the oxide (which is about 4).